A 50nm high-k poly silicon gate stack with a buried SiGe channel

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Authors
Jakschik, S.; Hoffmann, Thomas Y.; Cho, Hag-Ju; Veloso, Anabela; Loo, Roger; Hyun, S.; Sorada, H.; Inoue, A.; de Potter de ten Broeck, Muriel; Eneman, Geert; Severi, Simone; Absil, Philippe; Biesemans, Serge
Conference
International Symposium on VLSI Technology, Systems and Applications
Title
A 50nm high-k poly silicon gate stack with a buried SiGe channel
Publication type
Proceedings paper
Embargo date
9999-12-31
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