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A 50nm high-k poly silicon gate stack with a buried SiGe channel

dc.contributor.authorJakschik, S.
dc.contributor.authorHoffmann, Thomas Y.
dc.contributor.authorCho, Hag-Ju
dc.contributor.authorVeloso, Anabela
dc.contributor.authorLoo, Roger
dc.contributor.authorHyun, S.
dc.contributor.authorSorada, H.
dc.contributor.authorInoue, A.
dc.contributor.authorde Potter de ten Broeck, Muriel
dc.contributor.authorEneman, Geert
dc.contributor.authorSeveri, Simone
dc.contributor.authorAbsil, Philippe
dc.contributor.authorBiesemans, Serge
dc.date.accessioned2021-10-16T16:53:07Z
dc.date.available2021-10-16T16:53:07Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/12347
dc.sourceIIOimport
dc.titleA 50nm high-k poly silicon gate stack with a buried SiGe channel
dc.typeProceedings paper
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorLoo, Roger
dc.contributor.imecauthorde Potter de ten Broeck, Muriel
dc.contributor.imecauthorEneman, Geert
dc.contributor.imecauthorSeveri, Simone
dc.contributor.imecauthorAbsil, Philippe
dc.contributor.imecauthorBiesemans, Serge
dc.contributor.orcidimecLoo, Roger::0000-0003-3513-6058
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.conferenceInternational Symposium on VLSI Technology, Systems and Applications
dc.source.conferencedate23/04/2007
dc.source.conferencelocationHsinchu Taiwan
imec.availabilityPublished - open access


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