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High performance & CMOS integration friendly dual metal gate MOSFETs using TaN/Ru or TaN/W/Ru stacking multi-layers on HfLaO gate dielectric

dc.contributor.authorWang, X.P.
dc.contributor.authorLi, M.F.
dc.contributor.authorYu, HongYu
dc.contributor.authorYang, J.J.
dc.contributor.authorLoh, W.Y.
dc.contributor.authorZhu, C.X.
dc.contributor.authorDu, A.Y.
dc.contributor.authorTrigg, A.D.
dc.contributor.authorZhang, G.
dc.contributor.authorSik, H.W.
dc.contributor.authorRen, C.
dc.contributor.authorLim, Andy
dc.contributor.authorLee, Rinus
dc.contributor.authorYu, X.F.
dc.contributor.authorChen, J.D.
dc.contributor.authorChin, Albert
dc.contributor.authorYeo, Y.C.
dc.contributor.authorBiesemans, Serge
dc.contributor.authorChua, T.C.
dc.contributor.authorNouri, F.
dc.contributor.authorLo, Patrick
dc.contributor.authorKwong, D.L.
dc.date.accessioned2021-10-16T21:38:44Z
dc.date.available2021-10-16T21:38:44Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13212
dc.sourceIIOimport
dc.titleHigh performance & CMOS integration friendly dual metal gate MOSFETs using TaN/Ru or TaN/W/Ru stacking multi-layers on HfLaO gate dielectric
dc.typeProceedings paper
dc.contributor.imecauthorBiesemans, Serge
dc.source.peerreviewyes
dc.source.conferenceInternational Conference on Solid State Devices and Materials - SSDM
dc.source.conferencedate18/09/2006
dc.source.conferencelocationIbaraki Japan
imec.availabilityPublished - imec
imec.internalnotes


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