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Modeling the gate current 1/f noise and its application to advanced CMOS devices

dc.contributor.authorCrupi, F.
dc.contributor.authorMagnone, P.
dc.contributor.authorIannacone, G.
dc.contributor.authorGiusi, G.
dc.contributor.authorPace, C.
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-17T06:39:44Z
dc.date.available2021-10-17T06:39:44Z
dc.date.issued2008
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13573
dc.sourceIIOimport
dc.titleModeling the gate current 1/f noise and its application to advanced CMOS devices
dc.typeProceedings paper
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage420
dc.source.endpage423
dc.source.conference9th International Conference on Solid-State and Integrated-Circuit Technology - IC-SICT
dc.source.conferencedate20/10/2008
dc.source.conferencelocationBeijing China
imec.availabilityPublished - open access


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