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Cu plating of through-Si vias for 3D-stacked integrated circuits

dc.contributor.authorRadisic, Alex
dc.contributor.authorLuhn, Ole
dc.contributor.authorSwinnen, Bart
dc.contributor.authorBender, Hugo
dc.contributor.authorDrijbooms, Chris
dc.contributor.authorDoumen, Geert
dc.contributor.authorKellens, Kristof
dc.contributor.authorRuythooren, Wouter
dc.contributor.authorVereecken, Philippe
dc.date.accessioned2021-10-17T10:02:43Z
dc.date.available2021-10-17T10:02:43Z
dc.date.issued2008
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/14350
dc.sourceIIOimport
dc.titleCu plating of through-Si vias for 3D-stacked integrated circuits
dc.typeOral presentation
dc.contributor.imecauthorRadisic, Alex
dc.contributor.imecauthorSwinnen, Bart
dc.contributor.imecauthorBender, Hugo
dc.contributor.imecauthorDrijbooms, Chris
dc.contributor.imecauthorDoumen, Geert
dc.contributor.imecauthorKellens, Kristof
dc.contributor.imecauthorRuythooren, Wouter
dc.contributor.imecauthorVereecken, Philippe
dc.contributor.orcidimecVereecken, Philippe::0000-0003-4115-0075
dc.source.peerreviewno
dc.source.conferenceMRS Fall Meeting Symposium E: Materials and Technologies for 3-D Integration
dc.source.conferencedate1/12/2008
dc.source.conferencelocationBoston, MA USA
imec.availabilityPublished - imec


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