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Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

dc.contributor.authorRagnarsson, Lars-Ake
dc.contributor.authorLi, Zilan
dc.contributor.authorTseng, Joshua
dc.contributor.authorSchram, Tom
dc.contributor.authorRohr, Erika
dc.contributor.authorCho, Moon Ju
dc.contributor.authorKauerauf, Thomas
dc.contributor.authorConard, Thierry
dc.contributor.authorOkuno, Y.
dc.contributor.authorParvais, Bertrand
dc.contributor.authorAbsil, Philippe
dc.contributor.authorBiesemans, Serge
dc.contributor.authorHoffmann, Thomas Y.
dc.date.accessioned2021-10-18T02:08:09Z
dc.date.available2021-10-18T02:08:09Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16085
dc.sourceIIOimport
dc.titleUltra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization
dc.typeProceedings paper
dc.contributor.imecauthorRagnarsson, Lars-Ake
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorConard, Thierry
dc.contributor.imecauthorParvais, Bertrand
dc.contributor.imecauthorAbsil, Philippe
dc.contributor.imecauthorBiesemans, Serge
dc.contributor.orcidimecRagnarsson, Lars-Ake::0000-0003-1057-8140
dc.contributor.orcidimecConard, Thierry::0000-0002-4298-5851
dc.contributor.orcidimecParvais, Bertrand::0000-0003-0769-7069
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.source.peerreviewyes
dc.source.beginpage663
dc.source.endpage666
dc.source.conferenceIEEE International Electron Devices Meeting - IEDM
dc.source.conferencedate7/12/2009
dc.source.conferencelocationBaltimore, MD USA
imec.availabilityPublished - imec


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