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Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging

dc.contributor.authorSabuncuoglu Tezcan, Deniz
dc.contributor.authorDuval, Fabrice
dc.contributor.authorPhilipsen, Harold
dc.contributor.authorLuhn, Ole
dc.contributor.authorSoussan, Philippe
dc.contributor.authorSwinnen, Bart
dc.date.accessioned2021-10-18T02:32:27Z
dc.date.available2021-10-18T02:32:27Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16147
dc.sourceIIOimport
dc.titleScalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging
dc.typeProceedings paper
dc.contributor.imecauthorSabuncuoglu Tezcan, Deniz
dc.contributor.imecauthorDuval, Fabrice
dc.contributor.imecauthorPhilipsen, Harold
dc.contributor.imecauthorSoussan, Philippe
dc.contributor.imecauthorSwinnen, Bart
dc.contributor.orcidimecSabuncuoglu Tezcan, Deniz::0000-0002-9237-7862
dc.contributor.orcidimecPhilipsen, Harold::0000-0002-5029-1104
dc.contributor.orcidimecSoussan, Philippe::0000-0002-1347-6978
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage1159
dc.source.endpage1164
dc.source.conference59th Electronic Components and Technology Conference - ECTC
dc.source.conferencedate26/05/2009
dc.source.conferencelocationSan Diego, CA USA
imec.availabilityPublished - open access


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