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Cleaning and strip requirements for metal gate based CMOS integration

dc.contributor.authorSchram, Tom
dc.contributor.authorSebaai, Farid
dc.contributor.authorClaes, Martine
dc.contributor.authorVos, Rita
dc.contributor.authorWada, Masayuki
dc.contributor.authorAlbert, Johan
dc.contributor.authorRohr, Erika
dc.contributor.authorKubicek, Stefan
dc.date.accessioned2021-10-18T02:45:00Z
dc.date.available2021-10-18T02:45:00Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16179
dc.sourceIIOimport
dc.titleCleaning and strip requirements for metal gate based CMOS integration
dc.typeProceedings paper
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorSebaai, Farid
dc.contributor.imecauthorClaes, Martine
dc.contributor.imecauthorVos, Rita
dc.contributor.imecauthorKubicek, Stefan
dc.source.peerreviewyes
dc.source.beginpage17
dc.source.endpage28
dc.source.conferenceCleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing 11
dc.source.conferencedate4/10/2009
dc.source.conferencelocationVienna austria
imec.availabilityPublished - imec
imec.internalnotesECS Transactions; Vol. 25, issue 5


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