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3D Wafer level packaging: processes and materials for through silicon-vias and thin die embedding

dc.contributor.authorSoussan, Philippe
dc.contributor.authorSabuncuoglu Tezcan, Deniz
dc.contributor.authorIker, Francois
dc.contributor.authorRuythooren, Wouter
dc.contributor.authorSwinnen, Bart
dc.contributor.authorMajeed, Bivragh
dc.contributor.authorBeyne, Eric
dc.date.accessioned2021-10-18T03:19:35Z
dc.date.available2021-10-18T03:19:35Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16262
dc.sourceIIOimport
dc.title3D Wafer level packaging: processes and materials for through silicon-vias and thin die embedding
dc.typeProceedings paper
dc.contributor.imecauthorSoussan, Philippe
dc.contributor.imecauthorSabuncuoglu Tezcan, Deniz
dc.contributor.imecauthorRuythooren, Wouter
dc.contributor.imecauthorSwinnen, Bart
dc.contributor.imecauthorMajeed, Bivragh
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecSoussan, Philippe::0000-0002-1347-6978
dc.contributor.orcidimecSabuncuoglu Tezcan, Deniz::0000-0002-9237-7862
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.source.peerreviewno
dc.source.beginpage1112-E01-05
dc.source.conferenceMaterials and Technologies for 3-D Integration
dc.source.conferencedate1/12/2008
dc.source.conferencelocationBoston, MA USA
imec.availabilityPublished - imec
imec.internalnotesMRS Symposium Proceedings; Vol. 1112


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