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Optimization of polysilicon encapsulated LOCOS for 0.25 micron CMOS: correlation between cavity dimensions, mechanical stress, and gate oxide integrity

dc.contributor.authorBadenes, Gonçal
dc.contributor.authorRooyackers, Rita
dc.contributor.authorJones, S. K.
dc.contributor.authorBazley, D.
dc.contributor.authorBeanland, R.
dc.contributor.authorDe Wolf, Ingrid
dc.contributor.authorDeferm, Ludo
dc.date.accessioned2021-09-30T07:55:13Z
dc.date.available2021-09-30T07:55:13Z
dc.date.issued1997
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/1709
dc.sourceIIOimport
dc.titleOptimization of polysilicon encapsulated LOCOS for 0.25 micron CMOS: correlation between cavity dimensions, mechanical stress, and gate oxide integrity
dc.typeProceedings paper
dc.contributor.imecauthorDe Wolf, Ingrid
dc.contributor.imecauthorDeferm, Ludo
dc.contributor.orcidimecDe Wolf, Ingrid::0000-0003-3822-5953
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage467
dc.source.endpage477
dc.source.conferenceULSI Science and Technology 1997
dc.source.conferencedate5/05/1997
dc.source.conferencelocationMontréal Canada
imec.availabilityPublished - imec
imec.internalnotesECS Proceedings; Vol. 97-3


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