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A structured and scalable test access architecture for TSV-based 3D stacked ICs

dc.contributor.authorMarinissen, Erik Jan
dc.contributor.authorVerbree, Jouke
dc.contributor.authorKonijnenburg, Mario
dc.date.accessioned2021-10-18T18:51:57Z
dc.date.available2021-10-18T18:51:57Z
dc.date.issued2010-04
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17588
dc.sourceIIOimport
dc.titleA structured and scalable test access architecture for TSV-based 3D stacked ICs
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.imecauthorKonijnenburg, Mario
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.contributor.orcidimecKonijnenburg, Mario::0000-0001-8016-0888
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage269
dc.source.endpage274
dc.source.conference28th IEEE VLSI Test Symposium - VTS
dc.source.conferencedate19/04/2010
dc.source.conferencelocationSanta Cruz, CA USA
dc.identifier.urlhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5469556
imec.availabilityPublished - open access


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