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Test-architecture optimization for TSV-based 3D stacked ICs

dc.contributor.authorNoia, Brandon
dc.contributor.authorGoel, Sandeep Kumar
dc.contributor.authorChakrabarty, Krishnendu
dc.contributor.authorMarinissen, Erik Jan
dc.contributor.authorVerbree, Jouke
dc.date.accessioned2021-10-18T19:39:33Z
dc.date.available2021-10-18T19:39:33Z
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17707
dc.sourceIIOimport
dc.titleTest-architecture optimization for TSV-based 3D stacked ICs
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.beginpage24
dc.source.endpage29
dc.source.conferenceIEEE European Test Symposium - ETS
dc.source.conferencedate24/05/2010
dc.source.conferencelocationPrague Czech Republic
dc.identifier.urlhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5512787
imec.availabilityPublished - imec


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