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Activity profile driven simultaneous Vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs

dc.contributor.authorSathanur, Ashoka
dc.contributor.authorHuisken, Jos
dc.contributor.authorStuijt, Jan
dc.contributor.authorde Groot, Harmke
dc.date.accessioned2021-10-18T21:18:53Z
dc.date.available2021-10-18T21:18:53Z
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17951
dc.sourceIIOimport
dc.titleActivity profile driven simultaneous Vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs
dc.typeProceedings paper
dc.contributor.imecauthorStuijt, Jan
dc.contributor.orcidimecStuijt, Jan::0000-0001-6797-2339
dc.source.peerreviewno
dc.source.beginpage519
dc.source.endpage522
dc.source.conferenceIEEE International Conference on Electronics, Circuits and Systems - ICECS
dc.source.conferencedate12/12/2010
dc.source.conferencelocationAthens Greece
imec.availabilityPublished - imec


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