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FinFETs junctions optimization by conventional ion implantation for (sub-)22nm technology nodes circuit applications

dc.contributor.authorVeloso, Anabela
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorBrus, Stephan
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorAbsil, Philippe
dc.contributor.authorHoffmann, Thomas Y.
dc.date.accessioned2021-10-18T23:38:02Z
dc.date.available2021-10-18T23:38:02Z
dc.date.issued2010-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18253
dc.sourceIIOimport
dc.titleFinFETs junctions optimization by conventional ion implantation for (sub-)22nm technology nodes circuit applications
dc.typeProceedings paper
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorBrus, Stephan
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.imecauthorAbsil, Philippe
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.source.peerreviewyes
dc.source.beginpage1024
dc.source.endpage1025
dc.source.conferenceInternational Conference on Solid State Devices and Materials - SSDM
dc.source.conferencedate22/09/2010
dc.source.conferencelocationTokyo Japan
imec.availabilityPublished - imec


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