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Cost-effectiveness of wafer-to-wafer 3D chip stacking with matching pre-tested wafers

dc.contributor.authorVerbree, Jouke
dc.contributor.authorMarinissen, Erik Jan
dc.contributor.authorRoussel, Philippe
dc.contributor.authorVelenis, Dimitrios
dc.date.accessioned2021-10-18T23:38:57Z
dc.date.available2021-10-18T23:38:57Z
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18255
dc.sourceIIOimport
dc.titleCost-effectiveness of wafer-to-wafer 3D chip stacking with matching pre-tested wafers
dc.typeOral presentation
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.imecauthorRoussel, Philippe
dc.contributor.imecauthorVelenis, Dimitrios
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.contributor.orcidimecRoussel, Philippe::0000-0002-0402-8225
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.conference3D Integration Workshop at DATE 2010
dc.source.conferencedate12/03/2010
dc.source.conferencelocationDresden Germany
dc.identifier.urlhttp://www.date-conference.com/files/file/10-workshops/date10-3dws-digestv2-100330.pdf
imec.availabilityPublished - open access


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