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On-chip circuit for massively parallel BTI characterization

dc.contributor.authorda Silva, Mauricio Banasheski
dc.contributor.authorKaczer, Ben
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorWirth, Gilson I.
dc.contributor.authorGroeseneken, Guido
dc.date.accessioned2021-10-19T13:00:43Z
dc.date.available2021-10-19T13:00:43Z
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18762
dc.sourceIIOimport
dc.titleOn-chip circuit for massively parallel BTI characterization
dc.typeProceedings paper
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.source.peerreviewyes
dc.source.conferenceIEEE International Integrated Reliability Workshop - IIRW
dc.source.conferencedate16/10/2011
dc.source.conferencelocationLake Tahoe, CA USA
imec.availabilityPublished - imec


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