Show simple item record

Joint optimization of layout and litho for SRAM and Logic towards the 20 nm node, using 193i

dc.contributor.authorDe Bisschop, Peter
dc.contributor.authorLaenens, Bart
dc.contributor.authorIwase, Kazuya
dc.contributor.authorYao, Teruyoshi
dc.contributor.authorDusa, Mircea
dc.contributor.authorSmayling, M.
dc.date.accessioned2021-10-19T13:02:53Z
dc.date.available2021-10-19T13:02:53Z
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18774
dc.sourceIIOimport
dc.titleJoint optimization of layout and litho for SRAM and Logic towards the 20 nm node, using 193i
dc.typeProceedings paper
dc.contributor.imecauthorDe Bisschop, Peter
dc.contributor.imecauthorDusa, Mircea
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage79730B
dc.source.conferenceOptical Microlithography XXIV
dc.source.conferencedate27/02/2011
dc.source.conferencelocationSan Jose, CA USA
imec.availabilityPublished - open access
imec.internalnotesProceedings SPIE; Vol.7973


Files in this item

Thumbnail
Name:
21342.pdf
Size:
1.548Mb
Format:
PDF
View/open

This item appears in the following collection(s)

Show simple item record