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Simulation of advanced-LOCOS capability for sub-0.25 micron CMOS isolation

dc.contributor.authorJones, S. K.
dc.contributor.authorBazley, D. J.
dc.contributor.authorBeanland, R.
dc.contributor.authorBadenes, Gonçal
dc.contributor.authorScaife, B.
dc.date.accessioned2021-09-30T08:31:32Z
dc.date.available2021-09-30T08:31:32Z
dc.date.issued1997
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/1958
dc.sourceIIOimport
dc.titleSimulation of advanced-LOCOS capability for sub-0.25 micron CMOS isolation
dc.typeProceedings paper
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage185
dc.source.endpage188
dc.source.conference1997 International Conference on Simulation of Semiconductor Processes and Devices - SISPAD
dc.source.conferencedate8/09/1997
dc.source.conferencelocationCambridge, MA USA
imec.availabilityPublished - open access


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