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Logic scaling assessment in 20nm and beyond under electrical and litho constraints

dc.contributor.authorBadaroglu, Mustafa
dc.contributor.authorGarcia Bardon, Marie
dc.contributor.authorDobrovolny, Petr
dc.contributor.authorZuber, Paul
dc.contributor.authorMiranda Corbalan, Miguel
dc.date.accessioned2021-10-20T10:03:40Z
dc.date.available2021-10-20T10:03:40Z
dc.date.issued2012
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20327
dc.sourceIIOimport
dc.titleLogic scaling assessment in 20nm and beyond under electrical and litho constraints
dc.typeProceedings paper
dc.contributor.imecauthorBadaroglu, Mustafa
dc.contributor.imecauthorGarcia Bardon, Marie
dc.contributor.imecauthorDobrovolny, Petr
dc.contributor.imecauthorZuber, Paul
dc.contributor.orcidimecDobrovolny, Petr::0000-0002-1465-481X
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.conferenceIEEE Faible Tension Faible Consommation Conference - FTFC
dc.source.conferencedate6/06/2012
dc.source.conferencelocationParis France
imec.availabilityPublished - open access


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