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Wafer thinning and back side processing to enable 3D stacking

dc.contributor.authorDetalle, Mikael
dc.contributor.authorBogaerts, Lieve
dc.contributor.authorLa Manna, Antonio
dc.contributor.authorBuisson, Thibault
dc.contributor.authorVelenis, Dimitrios
dc.contributor.authorBeyne, Eric
dc.date.accessioned2021-10-20T10:41:32Z
dc.date.available2021-10-20T10:41:32Z
dc.date.issued2012
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20596
dc.sourceIIOimport
dc.titleWafer thinning and back side processing to enable 3D stacking
dc.typeProceedings paper
dc.contributor.imecauthorDetalle, Mikael
dc.contributor.imecauthorBogaerts, Lieve
dc.contributor.imecauthorLa Manna, Antonio
dc.contributor.imecauthorVelenis, Dimitrios
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.conference4th Electronics System Integration Technologies Conference - ESTC
dc.source.conferencedate17/09/2012
dc.source.conferencelocationAmsterdam The Netherlands
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6542113&queryText%3DWafer+thinning+and+back+side+processing+to+en
imec.availabilityPublished - open access


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