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DfT architecture and ATPG for interconnect tests of JEDEC wide-IO DRAM memory-on-Logic 2.5D/3D-stacks

dc.contributor.authorDeutsch, Sergej
dc.contributor.authorChickermane, Vivek
dc.contributor.authorKeller, Brion
dc.contributor.authorMukherjee, Subhasish
dc.contributor.authorSood, Navdeep
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-20T10:41:57Z
dc.date.available2021-10-20T10:41:57Z
dc.date.issued2012-05
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20598
dc.sourceIIOimport
dc.titleDfT architecture and ATPG for interconnect tests of JEDEC wide-IO DRAM memory-on-Logic 2.5D/3D-stacks
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.conferenceCadence CDNLive! EMEA
dc.source.conferencedate14/05/2012
dc.source.conferencelocationMunich Germany
imec.availabilityPublished - imec


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