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DfT insertion and interconnect test generation for 3D stacks with JEDEC wide-IO DRAM

dc.contributor.authorDeutsch, Sergej
dc.contributor.authorKeller, Brion
dc.contributor.authorChickermane, Vivek
dc.contributor.authorGoel, Sandeep K.
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-20T10:42:08Z
dc.date.available2021-10-20T10:42:08Z
dc.date.issued2012-05
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20599
dc.sourceIIOimport
dc.titleDfT insertion and interconnect test generation for 3D stacks with JEDEC wide-IO DRAM
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.conferenceIEEE North-Atlantic Test Workshop - NATW
dc.source.conferencedate9/05/2012
dc.source.conferencelocationWoburn, MA USA
imec.availabilityPublished - imec


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