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Wafer backside thinning process integrated with post-thinning clean and TSV exposure recess etch

dc.contributor.authorZhao, Ming
dc.contributor.authorHayakawa, Susumu
dc.contributor.authorNishida, Yoshiteru
dc.contributor.authorJourdain, Anne
dc.contributor.authorTabuchi, Tomotaka
dc.contributor.authorLeunissen, Peter
dc.date.accessioned2021-10-20T19:41:22Z
dc.date.available2021-10-20T19:41:22Z
dc.date.issued2012
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21930
dc.sourceIIOimport
dc.titleWafer backside thinning process integrated with post-thinning clean and TSV exposure recess etch
dc.typeProceedings paper
dc.contributor.imecauthorZhao, Ming
dc.contributor.imecauthorJourdain, Anne
dc.contributor.orcidimecZhao, Ming::0000-0002-0856-851X
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage865
dc.source.endpage870
dc.source.conferenceChina Semiconductor Technology International Conference - CSTIC
dc.source.conferencedate18/03/2012
dc.source.conferencelocationShanghai China
imec.availabilityPublished - open access
imec.internalnotesECS Transactions; Vol. 44, Issue 1


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