Show simple item record

Demonstration of integrating post-thinning clean and TSV exposure recess etch into a wafer backside thinning process

dc.contributor.authorZhao, Ming
dc.contributor.authorHayakawa, Susumu
dc.contributor.authorNishida, Yoshiteru
dc.contributor.authorJourdain, Anne
dc.contributor.authorTabuchi, Tomotaka
dc.contributor.authorLeunissen, Peter
dc.date.accessioned2021-10-20T19:41:53Z
dc.date.available2021-10-20T19:41:53Z
dc.date.issued2012
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21931
dc.sourceIIOimport
dc.titleDemonstration of integrating post-thinning clean and TSV exposure recess etch into a wafer backside thinning process
dc.typeProceedings paper
dc.contributor.imecauthorZhao, Ming
dc.contributor.imecauthorJourdain, Anne
dc.contributor.orcidimecZhao, Ming::0000-0002-0856-851X
dc.source.peerreviewyes
dc.source.conference4th Electronics System Integration Technology Conference - ESTC
dc.source.conferencedate17/09/2012
dc.source.conferencelocationAmsterdam The Netherlands
imec.availabilityPublished - imec


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following collection(s)

Show simple item record