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Generation rate analysis of different S/D junction engineering in scalted UTBOX 1-T DRAM

dc.contributor.authorNicoletti, Talitha
dc.contributor.authorSasaki, Katia R.A.
dc.contributor.authordos Santos, Sara D.
dc.contributor.authorMartino, Jao Antonio
dc.contributor.authorAoulaiche, Marc
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-21T10:27:07Z
dc.date.available2021-10-21T10:27:07Z
dc.date.issued2013
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/22862
dc.sourceIIOimport
dc.titleGeneration rate analysis of different S/D junction engineering in scalted UTBOX 1-T DRAM
dc.typeProceedings paper
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage195
dc.source.endpage201
dc.source.conferenceAdvanced Semiconductor-on-Isolator Technology and Related Physics 16
dc.source.conferencedate12/05/2013
dc.source.conferencelocationToronto Canada
imec.availabilityPublished - open access
imec.internalnotesECS Proceedings; Vol. 53; Issue 5


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