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Gate double patterning strategies for 10nm node FinFET devices

dc.contributor.authorHody, Hubert
dc.contributor.authorParaschiv, Vasile
dc.contributor.authorHellin, David
dc.contributor.authorVandeweyer, Tom
dc.contributor.authorBoccardi, Guillaume
dc.contributor.authorXu, Kaidong
dc.date.accessioned2021-10-22T02:00:42Z
dc.date.available2021-10-22T02:00:42Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23943
dc.sourceIIOimport
dc.titleGate double patterning strategies for 10nm node FinFET devices
dc.typeMeeting abstract
dc.contributor.imecauthorHody, Hubert
dc.contributor.imecauthorParaschiv, Vasile
dc.contributor.imecauthorHellin, David
dc.contributor.imecauthorVandeweyer, Tom
dc.contributor.imecauthorBoccardi, Guillaume
dc.contributor.orcidimecBoccardi, Guillaume::0000-0003-3226-4572
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage905407
dc.source.conferenceAdvanced Etch Technology for Nanopatterning III
dc.source.conferencedate23/02/2014
dc.source.conferencelocationSan Jose, CA USA
dc.identifier.urlhttp://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=1855822
imec.availabilityPublished - open access
imec.internalnotesProceedings of SPIE; Vol. 9054


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