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CDM ESD testing of a 3D TSV stacked IC chip

dc.contributor.authorNagata, Nagata
dc.contributor.authorTakaya, Satoshi
dc.contributor.authorIkeda, Hiroaki
dc.contributor.authorLinten, Dimitri
dc.contributor.authorScholz, Mirko
dc.contributor.authorChen, Shih-Hung
dc.contributor.authorHasegawa, Keiichi
dc.contributor.authorShintani, Taizo
dc.contributor.authorSawada, Masanori
dc.date.accessioned2021-10-22T04:11:48Z
dc.date.available2021-10-22T04:11:48Z
dc.date.issued2014-10
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24308
dc.sourceIIOimport
dc.titleCDM ESD testing of a 3D TSV stacked IC chip
dc.typeMeeting abstract
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage4
dc.source.conference5th IEEE International 3D-TEST Workshop
dc.source.conferencedate23/10/2014
dc.source.conferencelocationSeattle, WA USA
imec.availabilityPublished - imec


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