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STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance

dc.contributor.authorAppeltans, Raf
dc.contributor.authorCosemans, Stefan
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorVerkest, Diederik
dc.contributor.authorVan der Perre, Liesbet
dc.contributor.authorDehaene, Wim
dc.date.accessioned2021-10-22T18:30:28Z
dc.date.available2021-10-22T18:30:28Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24937
dc.sourceIIOimport
dc.titleSTT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance
dc.typeProceedings paper
dc.contributor.imecauthorAppeltans, Raf
dc.contributor.imecauthorCosemans, Stefan
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorDehaene, Wim
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage6
dc.source.conferenceIEEE Non-Volatile Memory System and Applications Symposium - NVMSA
dc.source.conferencedate19/08/2015
dc.source.conferencelocationHong Kong Hong Kong
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7304355
imec.availabilityPublished - imec


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