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An optimized poly-buffered LOCOS process for a 0.35 µm CMOS technology

dc.contributor.authorMieville, Jean-Paul
dc.contributor.authorRooyackers, Rita
dc.contributor.authorDeferm, Ludo
dc.date.accessioned2021-09-29T12:43:54Z
dc.date.available2021-09-29T12:43:54Z
dc.date.issued1994
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/257
dc.sourceIIOimport
dc.titleAn optimized poly-buffered LOCOS process for a 0.35 µm CMOS technology
dc.typeProceedings paper
dc.contributor.imecauthorDeferm, Ludo
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage199
dc.source.endpage202
dc.source.conference24th European Solid State Device Research Conference - ESSDERC
dc.source.conferencedate11/09/1994
dc.source.conferencelocationEdinburgh UK
imec.availabilityPublished - open access


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