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Through silicon via to FinFET noise coupling in 3-D integrated circuits

dc.contributor.authorRouhi Najaf Abadi, Alireza
dc.contributor.authorGuo, Wei
dc.contributor.authorSun, Xiao
dc.contributor.authorBen Ali, K.
dc.contributor.authorRaskin, J.P
dc.contributor.authorRack, M.
dc.contributor.authorRoda Neve, Cesar
dc.contributor.authorChoi, M.
dc.contributor.authorMoroz, V.
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorDe Wolf, Ingrid
dc.contributor.authorBeyne, Eric
dc.contributor.authorAbsil, Philippe
dc.date.accessioned2021-10-22T22:24:32Z
dc.date.available2021-10-22T22:24:32Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25841
dc.sourceIIOimport
dc.titleThrough silicon via to FinFET noise coupling in 3-D integrated circuits
dc.typeProceedings paper
dc.contributor.imecauthorGuo, Wei
dc.contributor.imecauthorSun, Xiao
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorDe Wolf, Ingrid
dc.contributor.imecauthorBeyne, Eric
dc.contributor.imecauthorAbsil, Philippe
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimecDe Wolf, Ingrid::0000-0003-3822-5953
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage4
dc.source.conferenceInternational Conference on IC Design and Technology - ICICDT
dc.source.conferencedate1/06/2015
dc.source.conferencelocationLeuven Belgium
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7165916
imec.availabilityPublished - open access


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