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At-speed inter-die interconnect test in 2.5D- and 3D-SICs

dc.contributor.authorShibin, Konstantin
dc.contributor.authorChickermane, Vivek
dc.contributor.authorKeller, Brion
dc.contributor.authorPapameletis, Christos
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-22T22:49:41Z
dc.date.available2021-10-22T22:49:41Z
dc.date.issued2015-10
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25900
dc.sourceIIOimport
dc.titleAt-speed inter-die interconnect test in 2.5D- and 3D-SICs
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.conferenceIEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST)
dc.source.conferencedate8/10/2015
dc.source.conferencelocationAnaheim, CA USA
dc.identifier.urlhttp://www.itctestweek.org/files/3DTest15Program.pdf
imec.availabilityPublished - imec
imec.internalnotes


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