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A 42 mW 200 fs-jitter 60 GHz sub-sampling PLL in 40 nm CMOS

dc.contributor.authorSzortyka, Viki
dc.contributor.authorShi, Qixian
dc.contributor.authorRaczkowski, Kuba
dc.contributor.authorParvais, Bertrand
dc.contributor.authorKuijk, Maarten
dc.contributor.authorWambacq, Piet
dc.date.accessioned2021-10-22T23:17:44Z
dc.date.available2021-10-22T23:17:44Z
dc.date.issued2015
dc.identifier.issn0018-9200
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25960
dc.sourceIIOimport
dc.titleA 42 mW 200 fs-jitter 60 GHz sub-sampling PLL in 40 nm CMOS
dc.typeJournal article
dc.contributor.imecauthorShi, Qixian
dc.contributor.imecauthorParvais, Bertrand
dc.contributor.imecauthorWambacq, Piet
dc.contributor.orcidimecParvais, Bertrand::0000-0003-0769-7069
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage2025
dc.source.endpage2036
dc.source.journalIEEE Journal of Solid-State Circuits
dc.source.issue9
dc.source.volume50
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7131584
imec.availabilityPublished - open access


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