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dc.contributor.authorPandey, R
dc.contributor.authorSchulte-Braucks, Christian
dc.contributor.authorSajjad, R.N.
dc.contributor.authorBarth, M.
dc.contributor.authorGhosh, R
dc.contributor.authorGrisafe, B.
dc.contributor.authorSharma, P.
dc.contributor.authorvon den Driesch, Niels
dc.contributor.authorVohra, Anurag
dc.contributor.authorRayner, R.
dc.contributor.authorLoo, Roger
dc.contributor.authorMantl, Siegfried
dc.contributor.authorBuca, Dan
dc.contributor.authorYeh, C.C.
dc.contributor.authorWu, C-H.
dc.contributor.authorTsai, Wilman
dc.contributor.authorAntoniadis, A.
dc.contributor.authorDatta, Suman
dc.date.accessioned2021-10-23T13:32:25Z
dc.date.available2021-10-23T13:32:25Z
dc.date.issued2016-12
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/27118
dc.sourceIIOimport
dc.titlePerformance benchmarking of p-type In0.65Ga0.35As/GaAs0.4Sb0.6 and Ge/Ge0.93Sn0.07 hetero-junction tunnel FETs for low voltage logic
dc.typeProceedings paper
dc.contributor.imecauthorVohra, Anurag
dc.contributor.imecauthorLoo, Roger
dc.contributor.orcidimecVohra, Anurag::0000-0002-2831-0719
dc.contributor.orcidimecLoo, Roger::0000-0003-3513-6058
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage520
dc.source.endpage523
dc.source.conferenceIEEE International Electron Devices Meeting - IEDM
dc.source.conferencedate3/12/2016
dc.source.conferencelocationSan Francisco, CA USA
imec.availabilityPublished - open access


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