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Large marginal 2D self-aligned via patterning for sub-5nm technology

dc.contributor.authorChoi, Suhyeong
dc.contributor.authorLee, Jae Uk
dc.contributor.authorBlanco, Victor
dc.contributor.authorDebacker, Peter
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorKim, Ryan Ryoung han
dc.contributor.authorShin, Youngsoo
dc.date.accessioned2021-10-24T03:28:37Z
dc.date.available2021-10-24T03:28:37Z
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/28030
dc.sourceIIOimport
dc.titleLarge marginal 2D self-aligned via patterning for sub-5nm technology
dc.typeProceedings paper
dc.contributor.imecauthorLee, Jae Uk
dc.contributor.imecauthorBlanco, Victor
dc.contributor.imecauthorDebacker, Peter
dc.contributor.imecauthorKim, Ryan Ryoung han
dc.contributor.orcidimecLee, Jae Uk::0000-0002-9434-5055
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.date.embargo9999-12-31
dc.identifier.doi10.1117/12.2257924
dc.source.peerreviewyes
dc.source.beginpage101480J
dc.source.conferenceDesign-Process-Technology Co-optimization for Manufacturability XI
dc.source.conferencedate26/02/2017
dc.source.conferencelocationSan Jose US
imec.availabilityPublished - open access
imec.internalnotesProceedings of SPIE; Vol. 10148


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