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Testing of 2.5D- and 3D-stacked integrated circuits

dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-24T08:46:05Z
dc.date.available2021-10-24T08:46:05Z
dc.date.issued2017-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/28918
dc.sourceIIOimport
dc.titleTesting of 2.5D- and 3D-stacked integrated circuits
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewno
dc.source.conferenceSEMICON Taiwan - IEEE International Test Conference Asia - ITC-Asia
dc.source.conferencedate13/09/2017
dc.source.conferencelocationTaipei Taiwan
imec.availabilityPublished - imec


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