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Lithographic strategies for 0.35µm poly gates for random logic applications

dc.contributor.authorOp de Beeck, Maaike
dc.contributor.authorVan Driessche, Veerle
dc.contributor.authorVan den hove, Luc
dc.contributor.authorDijkstra, H.
dc.date.accessioned2021-09-29T12:45:08Z
dc.date.available2021-09-29T12:45:08Z
dc.date.issued1994
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/289
dc.sourceIIOimport
dc.titleLithographic strategies for 0.35µm poly gates for random logic applications
dc.typeProceedings paper
dc.contributor.imecauthorOp de Beeck, Maaike
dc.contributor.imecauthorVan Driessche, Veerle
dc.contributor.imecauthorVan den hove, Luc
dc.contributor.orcidimecOp de Beeck, Maaike::0000-0002-2700-6432
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage407
dc.source.endpage421
dc.source.conferenceAdvances in Resist Technology and Processing XI
dc.source.conferencedate28/02/1994
dc.source.conferencelocationSan Jose, CA USA
imec.availabilityPublished - open access
imec.internalnotesProceedings of SPIE; Vol. 2195


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