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Thermal stability and switching performance metrics of top-pinned STT-MRAM devices with CMOS-compatible dual MgO MTJ stacks

dc.contributor.authorRao, Siddharth
dc.contributor.authorKim, Woojin
dc.contributor.authorCouet, Sebastien
dc.contributor.authorSwerts, Johan
dc.contributor.authorMertens, Sofie
dc.contributor.authorLin, Tsann
dc.contributor.authorSouriau, Laurent
dc.contributor.authorKundu, Shreya
dc.contributor.authorTsvetanova, Diana
dc.contributor.authorCrotti, Davide
dc.contributor.authorYasin, Farrukh
dc.contributor.authorSakhare, Sushil
dc.contributor.authorFurnemont, Arnaud
dc.contributor.authorKar, Gouri Sankar
dc.date.accessioned2021-10-24T11:54:39Z
dc.date.available2021-10-24T11:54:39Z
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/29270
dc.sourceIIOimport
dc.titleThermal stability and switching performance metrics of top-pinned STT-MRAM devices with CMOS-compatible dual MgO MTJ stacks
dc.typeOral presentation
dc.contributor.imecauthorRao, Siddharth
dc.contributor.imecauthorKim, Woojin
dc.contributor.imecauthorCouet, Sebastien
dc.contributor.imecauthorSwerts, Johan
dc.contributor.imecauthorMertens, Sofie
dc.contributor.imecauthorSouriau, Laurent
dc.contributor.imecauthorKundu, Shreya
dc.contributor.imecauthorTsvetanova, Diana
dc.contributor.imecauthorCrotti, Davide
dc.contributor.imecauthorYasin, Farrukh
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.orcidimecRao, Siddharth::0000-0001-6161-3052
dc.contributor.orcidimecCouet, Sebastien::0000-0001-6436-9593
dc.contributor.orcidimecMertens, Sofie::0000-0002-1482-6730
dc.contributor.orcidimecSouriau, Laurent::0000-0002-5138-5938
dc.contributor.orcidimecYasin, Farrukh::0000-0002-7295-0254
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.source.peerreviewno
dc.source.conferenceIntermag 2017
dc.source.conferencedate24/04/2017
dc.source.conferencelocationDublin Ireland
imec.availabilityPublished - imec
imec.internalnotesAccepted as poster


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