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Channel and gate stack charge trapping investigation in vertical 3D NAND devices with poly-silicon channel

dc.contributor.authorSubirats, Alexandre
dc.contributor.authorArreghini, Antonio
dc.contributor.authorBreuil, Laurent
dc.contributor.authorDegraeve, Robin
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorLinten, Dimitri
dc.contributor.authorFurnemont, Arnaud
dc.date.accessioned2021-10-24T14:24:40Z
dc.date.available2021-10-24T14:24:40Z
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/29520
dc.sourceIIOimport
dc.titleChannel and gate stack charge trapping investigation in vertical 3D NAND devices with poly-silicon channel
dc.typeProceedings paper
dc.contributor.imecauthorArreghini, Antonio
dc.contributor.imecauthorBreuil, Laurent
dc.contributor.imecauthorDegraeve, Robin
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.orcidimecArreghini, Antonio::0000-0002-7493-9681
dc.contributor.orcidimecBreuil, Laurent::0000-0003-2869-1651
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.source.peerreviewno
dc.source.conferenceInternational Workshop on Characterization and Modeling of Memory Devices - IWCM2
dc.source.conferencedate28/09/2017
dc.source.conferencelocationMilano Italy
imec.availabilityPublished - imec


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