Browsing Book chapters by imec author "2582ae04d02ff2073004169f4a934d0cbcf31120"
Now showing items 1-7 of 7
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3D design-for-test architecture
Marinissen, Erik Jan; Konijnenburg, Mario; Verbree, Jouke; Chi, Chun-Chuan; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias; Shibin, Konstantin; Keller, Brion; Chickermane, Vivek; Goel, Sandeep K. (2019-03) -
3D-COSTAR for 2.5D and 3D stacked IC cost optimization
Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan (2014-12) -
Cost modeling for 2.5D and 3D stacked ICs
Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan (2019-03) -
IEEE Std P1838: 3D test access standard under development
Cron, Adam; Marinissen, Erik Jan; Goel, Sandeep K.; McLaurin, Teresa; Bhatia, Sandeep (2019-03) -
Optimization of test-access architecture and test scheduling for 3D ICs
Deutsch, Sergej; Noia, Brandon; Chakrabarty, Krishnendu; Marinissen, Erik Jan (2019-03) -
Pre-Bond Testing Through Direct Probing of Large-Array Fine-Pitch Micro-Bumps
Marinissen, Erik Jan; De Wachter, Bart; Kiesewetter, Joerg; Smith, Ken (2019-03) -
Test and debug strategy for TSMC CoWoS stacking process-based heterogeneous 3D-IC: A silicon study
Goel, Sandeep K.; Adham, Saman; Wang, Min-Jer; Lee, Frank; Chickermane, Vivek; Keller, Brion; Valind, Thomas; Marinissen, Erik Jan (2019-03)