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dc.contributor.authorHuynen, Martijn
dc.contributor.authorDe Zutter, Daniel
dc.contributor.authorVande Ginste, Dries
dc.date.accessioned2021-10-25T20:07:29Z
dc.date.available2021-10-25T20:07:29Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/30932
dc.sourceIIOimport
dc.titleA fully 3-D BIE evaluation of the resistance and inductance of on-board and on-chip interconnects
dc.typeProceedings paper
dc.contributor.imecauthorHuynen, Martijn
dc.contributor.imecauthorDe Zutter, Daniel
dc.contributor.imecauthorVande Ginste, Dries
dc.contributor.orcidimecHuynen, Martijn::0000-0002-5168-9421
dc.contributor.orcidimecVande Ginste, Dries::0000-0002-0178-288X
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage4
dc.source.conferenceIEEE 22nd Workshop on Signal and Power Integrity - SPI2018
dc.source.conferencedate22/05/2018
dc.source.conferencelocationBrest France
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8401653
imec.availabilityPublished - open access
imec.internalnotesISBN 978-1-5386-2299-5


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