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Consideration of UFET architecture for the 5nm node and beyond logic transistor

dc.contributor.authorKumar Das, Utta
dc.contributor.authorEneman, Geert
dc.contributor.authorVelampati, Ravi
dc.contributor.authorChauhan, Y.
dc.contributor.authorJinesh, K.
dc.contributor.authorBhattacharya, T.
dc.date.accessioned2021-10-25T21:18:47Z
dc.date.available2021-10-25T21:18:47Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31091
dc.sourceIIOimport
dc.titleConsideration of UFET architecture for the 5nm node and beyond logic transistor
dc.typeProceedings paper
dc.contributor.imecauthorEneman, Geert
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.conferenceSilicon Nanoelectronics Workshop
dc.source.conferencedate17/06/2018
dc.source.conferencelocationHonolulu USA
imec.availabilityPublished - imec


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