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Track height reduction for standard-cell in below 5nm node: How low can you go?

dc.contributor.authorSherazi, Yasser
dc.contributor.authorChae, Jung Kyu
dc.contributor.authorDebacker, Peter
dc.contributor.authorMattii, Luca
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorGerousis, V.
dc.contributor.authorVerkest, Diederik
dc.contributor.authorMocuta, Anda
dc.contributor.authorKim, Ryan Ryoung han
dc.contributor.authorSpessot, Alessio
dc.contributor.authorRyckaert, Julien
dc.date.accessioned2021-10-26T03:42:48Z
dc.date.available2021-10-26T03:42:48Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31765
dc.sourceIIOimport
dc.titleTrack height reduction for standard-cell in below 5nm node: How low can you go?
dc.typeMeeting abstract
dc.contributor.imecauthorSherazi, Yasser
dc.contributor.imecauthorDebacker, Peter
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorKim, Ryan Ryoung han
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1058809
dc.source.conferenceDesign-Process-Technology Co-optimization for Manufacturability XII
dc.source.conferencedate25/02/2018
dc.source.conferencelocationSan Jose, CA USA
dc.identifier.urlhttps://doi.org/10.1117/12.2297191
imec.availabilityPublished - open access
imec.internalnotesProceedings of SPIE; Vol. 10588


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