Show simple item record

Influence of gate length on ESD performance for deep submicron CMOS technology

dc.contributor.authorBock, Karlheinz
dc.contributor.authorKeppens, Bart
dc.contributor.authorDe Heyn, Vincent
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorChing, L. Y.
dc.contributor.authorNaem, Abdalla
dc.date.accessioned2021-10-06T10:43:16Z
dc.date.available2021-10-06T10:43:16Z
dc.date.issued1999
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/3240
dc.sourceIIOimport
dc.titleInfluence of gate length on ESD performance for deep submicron CMOS technology
dc.typeProceedings paper
dc.contributor.imecauthorDe Heyn, Vincent
dc.contributor.imecauthorGroeseneken, Guido
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage95
dc.source.endpage104
dc.source.conferenceElectrical Overstress/Electrostatic Discharge Symposium Proceedings - EOS-ESD
dc.source.conferencedate28/09/1999
dc.source.conferencelocationOrlando, FL USA
imec.availabilityPublished - open access


Files in this item

Thumbnail
Name:
3201.pdf
Size:
1.127Mb
Format:
PDF
View/open

This item appears in the following collection(s)

Show simple item record