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Improvement of conduction in 3D NAND memory devices by channel and junction optimization

dc.contributor.authorArreghini, Antonio
dc.contributor.authorBanerjee, Kaustuv
dc.contributor.authorVerreck, Devin
dc.contributor.authorVadakupudhu Palayam, Senthil
dc.contributor.authorRosseel, Erik
dc.contributor.authorNyns, Laura
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorFurnemont, Arnaud
dc.date.accessioned2021-10-27T07:27:24Z
dc.date.available2021-10-27T07:27:24Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32459
dc.sourceIIOimport
dc.titleImprovement of conduction in 3D NAND memory devices by channel and junction optimization
dc.typeProceedings paper
dc.contributor.imecauthorArreghini, Antonio
dc.contributor.imecauthorBanerjee, Kaustuv
dc.contributor.imecauthorVerreck, Devin
dc.contributor.imecauthorVadakupudhu Palayam, Senthil
dc.contributor.imecauthorRosseel, Erik
dc.contributor.imecauthorNyns, Laura
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.orcidimecArreghini, Antonio::0000-0002-7493-9681
dc.contributor.orcidimecBanerjee, Kaustuv::0000-0001-8003-6211
dc.contributor.orcidimecVerreck, Devin::0000-0002-3833-5880
dc.contributor.orcidimecNyns, Laura::0000-0001-8220-870X
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.source.peerreviewyes
dc.source.beginpage140
dc.source.endpage143
dc.source.conferenceIEEE 11th International Memory Workshop 2019
dc.source.conferencedate12/05/2019
dc.source.conferencelocationMonterey, CA USA
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8739661
imec.availabilityPublished - imec


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