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Process, circuit and system co-optimization of wafer level co-integrated FinFET with vertical nanosheet selector for STT-MRAM applications

dc.contributor.authorHuynh Bao, Trong
dc.contributor.authorVeloso, Anabela
dc.contributor.authorMatagne, Philippe
dc.contributor.authorRyckaert, Julien
dc.contributor.authorCrotti, Davide
dc.contributor.authorYasin, Farrukh
dc.contributor.authorPerumkunnil, Manu
dc.contributor.authorSpessot, Alessio
dc.contributor.authorKar, Gouri Sankar
dc.contributor.authorMocuta, Anda
dc.contributor.authorFurnemont, Arnaud
dc.date.accessioned2021-10-27T10:41:37Z
dc.date.available2021-10-27T10:41:37Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/33189
dc.sourceIIOimport
dc.titleProcess, circuit and system co-optimization of wafer level co-integrated FinFET with vertical nanosheet selector for STT-MRAM applications
dc.typeProceedings paper
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorMatagne, Philippe
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorCrotti, Davide
dc.contributor.imecauthorYasin, Farrukh
dc.contributor.imecauthorPerumkunnil, Manu
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.orcidimecYasin, Farrukh::0000-0002-7295-0254
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage6
dc.source.conference2019 56th ACM/IEEE Design Automation Conference (DAC)
dc.source.conferencedate2/06/2019
dc.source.conferencelocationLas Vegas, NV USA
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8807022
imec.availabilityPublished - open access


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