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Gate-stack engineered NBTI improvements in high-voltage logic-for-memory high-k/metal gate devices
Publication:
Gate-stack engineered NBTI improvements in high-voltage logic-for-memory high-k/metal gate devices
Date
2019
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
O'Sullivan, Barry
;
Ritzenthaler, Romain
;
Rzepa, G
;
Wu, Zhicheng
;
Dentoni Litta, Eugenio
;
Richard, Olivier
;
Conard, Thierry
;
Machkaoutsan, Vladimir
;
Fazan, Pierre
;
Kim, Cheolgyu
;
Franco, Jacopo
;
Kaczer, Ben
;
Grasser, T
;
Spessot, Alessio
;
Linten, Dimitri
;
Horiguchi, Naoto
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1971
since deposited on 2021-10-27
430
item.page.metrics.field.last-week
Acq. date: 2025-10-25
Citations
Metrics
Views
1971
since deposited on 2021-10-27
430
item.page.metrics.field.last-week
Acq. date: 2025-10-25
Citations