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Buried power rails and back-side power grids: ARM CPU power delivery network design beyond 5nm

dc.contributor.authorPrasad, D.
dc.contributor.authorNibhanupudi, S.
dc.contributor.authorDas, S.
dc.contributor.authorZografos, Odysseas
dc.contributor.authorChehab, Bilal
dc.contributor.authorSarkar, Satadru
dc.contributor.authorBaert, Rogier
dc.contributor.authorRobinson, A.
dc.contributor.authorGupta, Anshul
dc.contributor.authorSpessot, Alessio
dc.contributor.authorDebacker, Peter
dc.contributor.authorVerkest, Diederik
dc.contributor.authorKulkarni, J.
dc.contributor.authorCline, B.
dc.contributor.authorSinha, S.
dc.date.accessioned2021-10-27T16:20:08Z
dc.date.available2021-10-27T16:20:08Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/33822
dc.sourceIIOimport
dc.titleBuried power rails and back-side power grids: ARM CPU power delivery network design beyond 5nm
dc.typeProceedings paper
dc.contributor.imecauthorZografos, Odysseas
dc.contributor.imecauthorChehab, Bilal
dc.contributor.imecauthorSarkar, Satadru
dc.contributor.imecauthorBaert, Rogier
dc.contributor.imecauthorGupta, Anshul
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorDebacker, Peter
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.orcidimecZografos, Odysseas::0000-0002-9998-8009
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage446
dc.source.endpage449
dc.source.conferenceIEEE International Electron Devices Meeting - IEDM 2019
dc.source.conferencedate9/12/2019
dc.source.conferencelocationSan Francisco, CA USA
imec.availabilityPublished - open access


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