dc.contributor.author | Thiam, Arame | |
dc.contributor.author | Wan, Danny | |
dc.contributor.author | Souriau, Laurent | |
dc.contributor.author | Babaei Gavan, Khashayar | |
dc.contributor.author | Rassoul, Nouredine | |
dc.contributor.author | Swerts, Johan | |
dc.contributor.author | Couet, Sebastien | |
dc.contributor.author | Raymenants, Eline | |
dc.contributor.author | Jussot, Julien | |
dc.contributor.author | Trivkovic, Darko | |
dc.contributor.author | Ercken, Monique | |
dc.contributor.author | Wilson, Chris | |
dc.contributor.author | Radu, Iuliana | |
dc.date.accessioned | 2021-10-27T19:35:05Z | |
dc.date.available | 2021-10-27T19:35:05Z | |
dc.date.issued | 2019 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/34116 | |
dc.source | IIOimport | |
dc.title | Patterning challenges for beyond 3nm logic devices: Example of an interconnected magnetic tunnel junction | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Thiam, Arame | |
dc.contributor.imecauthor | Wan, Danny | |
dc.contributor.imecauthor | Souriau, Laurent | |
dc.contributor.imecauthor | Babaei Gavan, Khashayar | |
dc.contributor.imecauthor | Rassoul, Nouredine | |
dc.contributor.imecauthor | Swerts, Johan | |
dc.contributor.imecauthor | Couet, Sebastien | |
dc.contributor.imecauthor | Raymenants, Eline | |
dc.contributor.imecauthor | Jussot, Julien | |
dc.contributor.imecauthor | Trivkovic, Darko | |
dc.contributor.imecauthor | Ercken, Monique | |
dc.contributor.imecauthor | Wilson, Chris | |
dc.contributor.imecauthor | Radu, Iuliana | |
dc.contributor.orcidimec | Wan, Danny::0000-0003-4847-3184 | |
dc.contributor.orcidimec | Souriau, Laurent::0000-0002-5138-5938 | |
dc.contributor.orcidimec | Rassoul, Nouredine::0000-0001-9489-3396 | |
dc.contributor.orcidimec | Couet, Sebastien::0000-0001-6436-9593 | |
dc.contributor.orcidimec | Jussot, Julien::0000-0002-2484-3462 | |
dc.contributor.orcidimec | Radu, Iuliana::0000-0002-7230-7218 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 109580Y | |
dc.source.conference | Novel Patterning Technologies for Semiconductors, MEMS/NEMS, and MOEMS 2019 | |
dc.source.conferencedate | 24/02/2019 | |
dc.source.conferencelocation | San Jose, CA USA | |
dc.identifier.url | https://doi.org/10.1117/12.2515086 | |
imec.availability | Published - imec | |
imec.internalnotes | Proceedings of SPIE; Vol. 10958 | |