Authors

Vega Gonzalez, Victor; Wilson, Chris; Briggs, Basoene; Decoster, Stefan; Versluijs, Janko; Lesniewska, Alicja; Paolillo, Sara; Baert, Rogier; Puliyalil, Harinarayanan; Bekaert, Joost; Kesters, Els; Le, Quoc Toan; Lorant, Christophe; Varela Pedreira, Olalla; Teugels, Lieve; Heylen, Nancy; El-Mekki, Zaid; van der Veen, Marleen; Webers, Tomas; Vats, Hemant; Rynders, Luc; Cupak, Miroslav; Lee, Jae Uk; Drissi, Youssef; Halipre, Luc; Charley, Anne-Laure; Verdonck, Patrick; Witters, Thomas; Van Gompel, Sander; Kimura, Yosuke; Jourdan, Nicolas; Ciofi, Ivan; Gupta, Anshul; Contino, Antonino; Boccardi, Guillaume; Lariviere, Stephane; Dupas, Luc; De Wachter, Bart; Vancoille, Eric; Lazzarino, Frederic; Ercken, Monique; Debacker, Peter; Kim, Ryan Ryoung han; Trivkovic, Darko; Croes, Kristof; Leray, Philippe; Dillemans, Leander; Chen, Yi-Fan; Tokei, Zsolt

Conference

IEEE International Electron Devices Meeting - IEDM

Title

Three-layer BEOL process integration with supervia and self-aligned-block options for the 3nm node

Publication type

Proceedings paper

Embargo date

9999-12-31