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dc.contributor.authorVerreck, Devin
dc.contributor.authorArreghini, Antonio
dc.contributor.authorBastos, Joao
dc.contributor.authorSchanovsky, Franz
dc.contributor.authorMitterbauer, Ferdinand
dc.contributor.authorKernstock, C.
dc.contributor.authorKarner, Markus
dc.contributor.authorDegraeve, Robin
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorFurnemont, Arnaud
dc.date.accessioned2021-10-27T22:41:20Z
dc.date.available2021-10-27T22:41:20Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/34376
dc.sourceIIOimport
dc.titleQuantitative 3-D model to explain large single trap charge variability in vertical NAND memory
dc.typeProceedings paper
dc.contributor.imecauthorVerreck, Devin
dc.contributor.imecauthorArreghini, Antonio
dc.contributor.imecauthorBastos, Joao
dc.contributor.imecauthorDegraeve, Robin
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.orcidimecVerreck, Devin::0000-0002-3833-5880
dc.contributor.orcidimecArreghini, Antonio::0000-0002-7493-9681
dc.contributor.orcidimecBastos, Joao::0000-0002-8877-9850
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage755
dc.source.endpage758
dc.source.conferenceIEEE International Electron Devices Meeting - IEDM
dc.source.conferencedate7/12/2019
dc.source.conferencelocationSan Francisco, CA USA
imec.availabilityPublished - open access


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